K60P100M100SF2RM Datasheet, PDF (312/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
13.1.2.3.1 Wait Mode
Wait mode is entered when the ARM core enters the sleep-now or sleep-on-exit modes.
The ARM CPU enters a low-power state in which it is not clocked, but peripherals
continue to be clocked provided they are enabled and clock gating to the peripheral is
enabled via the SIM.
When an interrupt request occurs, the CPU exits wait mode and resumes processing,
beginning with the stacking operations leading to the interrupt service routine.
An asserted RESET pin or LVD (if the LVD system is enabled) exits wait mode,
returning the device to normal run mode.
13.1.2.3.2 Very Low Power Wait (VLPW) Mode
VLPW is entered by the entering the “sleep-now" or "sleep-on-exit” mode while the
MCU is in the very low power run (VLPR) mode and configured appropriately.
In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state,
the regulator is designed to supply enough current to the MCU over a reduced frequency.
To further reduce power in this mode, disable the clocks to unused modules by clearing
the peripherals' corresponding clock gating control bits in the SIM.
VLPR mode restrictions also apply to VLPW.
VLPW mode provides the option to return to full-regulated normal run mode if any
enabled interrupt occurs. This is done by setting the low power wake up on interrupt
(LPWUI) bit in the PMCTRL register. Wait for REGONS status to set before increasing
the frequency.
If the LPWUI bit is clear when the interrupt from VLPW occurs, the device returns to
VLPR mode to execute the interrupt service routine. Wait for VLPRS status to set before
transitioning to other power modes.
An asserted RESET pin or a watchdog timeout exits VLPW and clears the RUNM and
WAITE bits. This returns the regulator to run regulation and the device to normal run
mode.
13.1.2.4 Stop Modes
This device contains a variety of stop modes to meet your application needs. The stop
modes range from: stopped CPU where all states are saved and certain asynchronous
mode peripherals are operating to only I/Os are held, a small register file is retained, and
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
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Freescale Semiconductor, Inc.