K60P100M100SF2RM Datasheet, PDF (1394/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

DSPI Signal Descriptions
49.1.4.5 Debug Mode
Debug mode is used for system development and debugging. The MCR[FRZ] bit controls
DSPI behavior in the debug mode. If the bit is set, the DSPI stops all serial transfers,
when the MCU is in debug mode. If the bit is cleared, the MCU debug mode has no
effect on the DSPI.
49.2 DSPI Signal Descriptions
This section provides the DSPI signals description.
The following table lists the signals that may connect off chip depending on device
implementation.
Table 49-1. DSPI Signal Descriptions
Signal
Description
I/O
PCS0/SS
Master mode: Peripheral Chip Select 0 output
I/O
Slave mode: Slave Select input
PCS[3:1]
Master mode: Peripheral Chip Select 1 - 3
O
Slave mode: Unused
PCS4
Master mode: Peripheral Chip Select 4
O
Slave mode: Unused
PCS5/ PCSS
Master mode: Peripheral Chip Select 5 /
O
Peripheral Chip Select Strobe
Slave mode: Unused
SIN
Serial Data In
I
SOUT
Serial Data Out
O
SCK
Master mode: Serial Clock (output)
I/O
Slave mode: Serial Clock (input)
49.2.1 PCS0/SS — Peripheral Chip Select/Slave Select
In master mode, the PCS0 signal is a Peripheral Chip Select output that selects which
slave device the current transmission is intended for.
In slave mode, the active low SS signal is a Slave Select input signal that allows a SPI
master to select the DSPI as the target for transmission.
1394
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.