K60P100M100SF2RM Datasheet, PDF (1684/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
Absolute
address
(hex)
I2S memory map (continued)
Register name
Width
(in bits)
Access
Reset value
4002_F018 I2S Interrupt Enable Register (I2S0_IER)
32
R/W 0000_3003h
4002_F01C I2S Transmit Configuration Register (I2S0_TCR)
32
R/W 0000_0200h
4002_F020 I2S Receive Configuration Register (I2S0_RCR)
32
R/W 0000_0200h
4002_F024 I2S Transmit Clock Control Registers (I2S0_TCCR)
32
R/W 0004_0000h
4002_F028 I2S Receive Clock Control Registers (I2S0_RCCR)
32
R/W 0004_0000h
4002_F02C I2S FIFO Control/Status Register (I2S0_FCSR)
32
R/W 0081_0081h
4002_F038 I2S AC97 Control Register (I2S0_ACNT)
32
R/W 0000_0000h
4002_F03C I2S AC97 Command Address Register (I2S0_ACADD)
32
R/W 0000_0000h
4002_F040 I2S AC97 Command Data Register (I2S0_ACDAT)
32
R/W 0000_0000h
4002_F044 I2S AC97 Tag Register (I2S0_ATAG)
32
R/W 0000_0000h
4002_F048 I2S Transmit Time Slot Mask Register (I2S0_TMSK)
32
R/W 0000_0000h
4002_F04C I2S Receive Time Slot Mask Register (I2S0_RMSK)
32
R/W 0000_0000h
4002_F050 I2S AC97 Channel Status Register (I2S0_ACCST)
4002_F054 I2S AC97 Channel Enable Register (I2S0_ACCEN)
4002_F058 I2S AC97 Channel Disable Register (I2S0_ACCDIS)
32
R
0000_0000h
W
32
(always
reads
0000_0000h
zero)
W
32
(always
reads
0000_0000h
zero)
Section/
page
53.3.7/
1695
53.3.8/
1699
53.3.9/
1701
53.3.10/
1703
53.3.11/
1705
53.3.12/
1706
53.3.13/
1712
53.3.14/
1713
53.3.15/
1714
53.3.16/
1714
53.3.17/
1715
53.3.18/
1715
53.3.19/
1716
53.3.20/
1716
53.3.21/
1717
1684
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.