K60P100M100SF2RM Datasheet, PDF (392/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
MPU_RGDAACn field descriptions (continued)
Field
25
M4RE
24
M4WE
23
Reserved
22–21
M3SM
Description
0 Bus master 5 writes terminate with an access error and the write is not performed
1 Bus master 5 writes allowed
Bus master 4 read enable.
0 Bus master 4 reads terminate with an access error and the read is not performed
1 Bus master 4 reads allowed
Bus master 4 write enable
0 Bus master 4 writes terminate with an access error and the write is not performed
1 Bus master 4 writes allowed
This field is reserved.
This bit must be written with a zero.
Bus master 3 supervisor mode access control
Defines the access controls for bus master 3 in supervisor mode
20–18
M3UM
00 r/w/x; read, write and execute allowed
01 r/x; read and execute allowed, but no write
10 r/w; read and write allowed, but no execute
11 Same as user mode defined in M3UM
Bus master 3 user mode access control
Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions.
17
Reserved
16–15
M2SM
14–12
M2UM
11
Reserved
10–9
M1SM
8–6
M1UM
5
Reserved
0 An attempted access of that mode may be terminated with an access error (if not allowed by another
descriptor) and the access not performed.
1 Allows the given access type to occur
This field is reserved.
This bit must be written with a zero.
Bus master 2 supervisor mode access control
See M3SM description.
Bus master 2 user mode access control
See M3UM description.
This field is reserved.
This bit must be written with a zero.
Bus master 1 supervisor mode access control
See M3SM description.
Bus master 1 user mode access control
See M3UM description.
This field is reserved.
This bit must be written with a zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
392
Freescale Semiconductor, Inc.