K60P100M100SF2RM Datasheet, PDF (1605/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
20
DTOEIEN
19
CIEIEN
18
CEBEIEN
17
CCEIEN
16
CTOEIEN
15–9
Reserved
8
CINTIEN
7
CRMIEN
6
CINSIEN
5
BRRIEN
4
BWRIEN
3
DINTIEN
Chapter 52 Secured digital host controller (SDHC)
SDHC_IRQSIGEN field descriptions (continued)
0b Masked
1b Enabled
Data Timeout Error Interrupt Enable
Description
0b Masked
1b Enabled
Command Index Error Interrupt Enable
0b Masked
1b Enabled
Command End Bit Error Interrupt Enable
0b Masked
1b Enabled
Command CRC Error Interrupt Enable
0b Masked
1b Enabled
Command Timeout Error Interrupt Enable
0b Masked
1b Enabled
This read-only field is reserved and always has the value zero.
Card Interrupt Enable
0b Masked
1b Enabled
Card Removal Interrupt Enable
0b Masked
1b Enabled
Card Insertion Interrupt Enable
0b Masked
1b Enabled
Buffer Read Ready Interrupt Enable
0b Masked
1b Enabled
Buffer Write Ready Interrupt Enable
0b Masked
1b Enabled
DMA Interrupt Enable
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1605