K60P100M100SF2RM Datasheet, PDF (4/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
3.2 Core modules................................................................................................................................................................69
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................69
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................72
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................78
3.2.4 JTAG Controller Configuration...................................................................................................................79
3.3 System modules............................................................................................................................................................80
3.3.1 SIM Configuration.......................................................................................................................................80
3.3.2 Mode Controller Configuration...................................................................................................................81
3.3.3 PMC Configuration......................................................................................................................................81
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................82
3.3.5 MCM Configuration....................................................................................................................................84
3.3.6 Crossbar Switch Configuration....................................................................................................................84
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................87
3.3.8 Peripheral Bridge Configuration..................................................................................................................89
3.3.9 DMA request multiplexer configuration......................................................................................................91
3.3.10 DMA Controller Configuration...................................................................................................................94
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................95
3.3.12 Watchdog Configuration..............................................................................................................................96
3.4 Clock Modules..............................................................................................................................................................97
3.4.1 MCG Configuration.....................................................................................................................................97
3.4.2 OSC Configuration......................................................................................................................................98
3.4.3 RTC OSC configuration...............................................................................................................................99
3.5 Memories and Memory Interfaces................................................................................................................................99
3.5.1 Flash Memory Configuration.......................................................................................................................99
3.5.2 Flash Memory Controller Configuration.....................................................................................................103
3.5.3 SRAM Configuration...................................................................................................................................104
3.5.4 SRAM Controller Configuration.................................................................................................................108
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
4
Freescale Semiconductor, Inc.