K60P100M100SF2RM Datasheet, PDF (1630/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
Table 52-35. Format of the ADMA1 descriptor table (continued)
Act2
0
0
1
1
Act1
0
1
0
1
Symbol
nop
set
tran
link
Comment
No operation
Set data length
Transfer data
Link descriptor
31-28
27-12
Don't care
0000
Data length
Data address
Descriptor address
Valid
End
Int
Valid = 1 indicates this line of descriptor is effective. If Valid = 0 generate ADMA error
Interrupt and stop ADMA.
End = 1 indicates current descriptor is the ending one.
Int = 1 generates DMA interrupt when this descriptor is processed.
System Address Register points to
the head node of Descriptor Table
Advanced DMA
System Address Register
Data Length (invisible)
Data Address (invisible)
Flags
State
Machine
SDMA
DMA Interrupt
Transfer Complete
Block Gap Event
System Memory
Descriptor Table
Address/Length Attribute
Address
Tran
Address
Link
Address/Length
Data Length
Address
Attribute
Set
Tran, End
Page Data
Page Data
Figure 52-32. Concept and access method of ADMA1 descriptor table
Address field
63
32
32-bit address
Table 52-36. Format of the ADMA2 descriptor table
Length
31
16-bit length
Reserved
16 15
0000000000
06 05
Act2
04
Act1
Attribute field
03
02
01
0
Int End
00
Valid
Act2
0
0
1
1
Act1
0
1
0
1
Symbol
nop
rsv
tran
link
Comment
No operation
Reserved
Transfer data
Link descriptor
Operation
Don't care
Same as nop. Read this line and
go to next one
Transfer data with address and
length set in this descriptor line
Link to another descriptor
Table continues on the next page...
1630
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.