K60P100M100SF2RM Datasheet, PDF (200/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Boot
reprogram the option byte in flash to change the FOPT values that are used for
subsequent resets. For more details on programming the option byte, refer to the flash
memory chapter.
The MCU uses the FTFL_FOPT register bits to configure the device at reset as shown in
the following table.
Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions
Bit
Num
Field
7-2 Reserved
1
EZPORT_DIS
0
LPBOOT
Value
Definition
Reserved for future expansion.
0
EzPort operation is disabled. The device always boots to normal CPU execution
and the state of EZP_CS signal during reset is ignored. This option avoids
inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI
function.
1
EzPort operation is enabled. The state of EZP_CS pin during reset determines if
device enters EzPort mode.
0
Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured
at reset exit for higher divide values that produce lower power consumption at
reset exit.
• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)
are 0x7 (divide by 8)
• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are
0xF (divide by 16)
1
Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at
reset exit for higher frequency values that produce faster operating frequencies at
reset exit.
• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)
are 0x0 (divide by 1)
• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are
0x1 (divide by 2)
6.3.4 Boot sequence
At power up, the on-chip regulator holds the system in a POR state until the input supply
is above the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Mode Controller reset logic then controls a sequence to exit reset.
1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCG is enabled in its default clocking mode.
2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus
Clocks that do not have clock gate control).
3. The system reset on internal logic continues to be held, but the Flash Controller is
released from reset and begins initialization operation while the Mode Control logic
continues to drive the RESET pin out low for a count of ~128 Bus Clock cycles.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
200
Freescale Semiconductor, Inc.