K60P100M100SF2RM Datasheet, PDF (1403/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Addresses: SPI0_CTAR0 is 4002_C000h base + Ch offset = 4002_C00Ch
SPI0_CTAR1 is 4002_C000h base + 10h offset = 4002_C010h
SPI1_CTAR0 is 4002_D000h base + Ch offset = 4002_D00Ch
SPI1_CTAR1 is 4002_D000h base + 10h offset = 4002_D010h
SPI2_CTAR0 is 400A_C000h base + Ch offset = 400A_C00Ch
SPI2_CTAR1 is 400A_C000h base + 10h offset = 400A_C010h
Bit 31
30
29
28
27
26
25
24
23
22
R
DBR
W
FMSZ
PCSSCK
21
20
PASC
Chapter 49 SPI (DSPI)
19
18
17
16
PDT
PBR
Reset 0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Bit 15
R
W
Reset 0
Field
31
DBR
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSSCK
ASC
DT
BR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPIx_CTARn field descriptions
Double Baud Rate
Description
Doubles the effective baud rate of the Serial Communications Clock (SCK). This field is used only in
master mode. It effectively halves the Baud Rate division ratio, supporting faster frequencies, and odd
division ratios for the Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
Serial Communications Clock (SCK) depends on the value in the Baud Rate Prescaler and the Clock
Phase bit as listed in the following table. See the BR field description for details on how to compute the
baud rate.
Table 49-32. DSPI SCK Duty Cycle
DBR
0
1
1
1
1
1
1
1
1
CPHA
any
0
0
0
0
1
1
1
1
PBR
any
00
01
10
11
00
01
10
11
SCK Duty Cycle
50/50
50/50
33/66
40/60
43/57
50/50
66/33
60/40
57/43
0 The baud rate is computed normally with a 50/50 duty cycle.
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1403