K60P100M100SF2RM Datasheet, PDF (1138/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
ENET_EIR field descriptions (continued)
Field
18
PLR
17
WAKEUP
16
TS_AVAIL
15
TS_TIMER
14–0
Reserved
Payload receive error
Description
Indicates a frame was received with a payload length error. See Frame Length/Type Verification: Payload
Length Check for more information.
Node wake-up request indication
Read-only status bit to indicate that a magic packet has been detected. Will act only if ECR[MAGICEN] is
set.
Transmit timestamp available
Indicates that the timestamp of the last transmitted timing frame is available in the ATSTMP register.
Timestamp timer
The adjustable timer reached the period event. A period event interrupt can be generated if
ATCR[PEREN] is set and the timer wraps according to the periodic setting in the ATPER register. Set the
timer period value before setting ATCR[PEREN].
This read-only field is reserved and always has the value zero.
44.3.2 Interrupt Mask Register (ENET_EIMR)
EIMR controls which interrupt events are allowed to generate actual interrupts. A
hardware reset clears this register. If the corresponding bits in the EIR and EIMR
registers are set, an interrupt is generated. The interrupt signal remains asserted until a 1
is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
Address: ENET_EIMR is 400C_0000h base + 8h offset = 400C_0008h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
W
TXF TXB RXF RXB MII
LC RL UN PLR
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1138
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.