K60P100M100SF2RM Datasheet, PDF (84/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

System modules
up the MCU from any non-VLLSx mode with the NMI function selected in its port control register asserts an NMI exception
on low power mode recovery. The same occurs when recovering from VLLSx modes if EzPort is disabled; otherwise,
EzPort mode is entered. See the "EzPort Configuration" section in this chapter for more information.
2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag
as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
3.3.5 MCM Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
PPB
Transfers
Miscellaneous
Control Module
(MCM)
Figure 3-9. MCM configuration
Table 3-14. Reference links to related information
Topic
Full description
System memory map
Clocking
Power management
Transfers
Private Peripheral Bus
(PPB)
Related module
Miscellaneous control
module (MCM)
ARM Cortex-M4 core
Reference
MCM
System memory map
Clock distribution
Power management
ARM Cortex-M4 core
3.3.6 Crossbar Switch Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
84
Freescale Semiconductor, Inc.