K60P100M100SF2RM Datasheet, PDF (1098/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
CMT_PPS field descriptions (continued)
Field
Description
The primary prescaler divides the CMT clock to generate the Intermediate Frequency clock enable to the
secondary prescaler.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bus Clock ÷ 1
Bus Clock ÷ 2
Bus Clock ÷ 3
Bus Clock ÷ 4
Bus Clock ÷ 5
Bus Clock ÷ 6
Bus Clock ÷ 7
Bus Clock ÷ 8
Bus Clock ÷ 9
Bus Clock ÷ 10
Bus Clock ÷ 11
Bus Clock ÷ 12
Bus Clock ÷ 13
Bus Clock ÷ 14
Bus Clock ÷ 15
Bus Clock ÷ 16
42.6.12 CMT Direct Memory Access (CMT_DMA)
This register is used to enable/disable direct memory access (DMA).
Address: CMT_DMA is 4006_2000h base + Bh offset = 4006_200Bh
Bit
7
6
5
4
3
2
Read
0
Write
Reset
0
0
0
0
0
0
CMT_DMA field descriptions
Field
7–1
Reserved
0
DMA
Description
This read-only field is reserved and always has the value zero.
DMA Enable
This bit enables the DMA protocol.
Table continues on the next page...
1
0
DMA
0
0
1098
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.