K60P100M100SF2RM Datasheet, PDF (295/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
31–3
Reserved
2
MPU
1
DMA
0
FLEXBUS
Chapter 12 System integration module (SIM)
SIM_SCGC7 field descriptions
Description
This read-only field is reserved and always has the value zero.
MPU Clock Gate Control
This bit controls the clock gate to the MPU module.
0 Clock disabled
1 Clock enabled
DMA Clock Gate Control
This bit controls the clock gate to the DMA module.
0 Clock disabled
1 Clock enabled
FlexBus Clock Gate Control
This bit controls the clock gate to the FlexBus module.
0 Clock disabled
1 Clock enabled
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)
The CLKDIV1 register cannot be written to when the device is in VLPR mode.
Address: SIM_CLKDIV1 is 4004_7000h base + 1044h offset = 4004_8044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
OUTDIV1 OUTDIV2 OUTDIV3 OUTDIV4
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
Field
31–28
OUTDIV1
SIM_CLKDIV1 field descriptions
Clock 1 output divider value
Description
This field sets the divide value for the core/system clock. At the end of reset, it is loaded with either 0000
or 0111 depending on FTFL_FOPT[LPBOOT].
0000
0001
0010
0011
Divide-by-1.
Divide-by-2.
Divide-by-3.
Divide-by-4.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
295