K60P100M100SF2RM Datasheet, PDF (735/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TBST
FB_TSIZ[1:0]
Address
Add
Data
Add+1
Add+1 Data
AA=1
AA=0
AA=1
AA=0
TSIZ = 00
Add+2
Add+2 Data
TSIZ = 01
Add+3
Add+3 Data
Figure 29-48. 32-bit-Write Burst-Inhibited to 8-Bit Port (No Wait States)
The following figure illustrates another read burst transfer, but in this case a wait state is
added between individual beats.
Note
CSCRn[WS] determines the number of wait states in the first
beat. However, for subsequent beats, the CSCRn[WS] (or
CSCRn[SWS] if CSCRn[SWSEN] is set) determines the
number of wait states.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
735