K60P100M100SF2RM Datasheet, PDF (232/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Pinout
Table 10-1. Reference links to related information (continued)
Topic
Clocking
Register access
Related module
Peripheral bus
controller
Reference
Clock Distribution
Peripheral bridge
10.2.1 Port control and interrupt module features
• Five 32-pin ports
NOTE
Not all pins are available on the device. See the following
section for details.
• Each 32-pin port is assigned one interrupt.
• The digital filter option has two clock source options: bus clock and 1-kHz LPO. The
1-kHz LPO option gives users this feature in low power modes.
• The digital filter is configurable from 1 to 32 clock cycles when enabled.
10.2.2 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx]
bits in the SIM module. These bits are cleared after any reset, which disables the clock to
the corresponding module to conserve power. Prior to initializing the corresponding
module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off
the clock, make sure to disable the module. For more details, refer to the clock
distribution chapter.
10.2.3 Signal multiplexing constraints
1. A given peripheral function must be assigned to a maximum of one package pin. Do
not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in
closest proximity to each other.
10.3 Pinout
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
232
Freescale Semiconductor, Inc.