K60P100M100SF2RM Datasheet, PDF (993/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 39 FlexTimer (FTM)
Firstly the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block (see the following figure). When there is a state
change in the input signal, the 5-bit counter is reset and starts counting up. As long as the
new state is stable on the input, the counter continues to increment. If the 5-bit counter
overflows (the counter exceeds the value of the CHnFVAL[3:0] bits), the state change of
the input signal is validated. It is then transmitted as a pulse edge to the edge detector.
channel (n) input after
the synchronizer
Logic to control
the filter counter
divided by 4
5-bit up counter
CHnFVAL[3:0]
Logic to define
the filter output
S
Q
C
CLK
filter output
system clock
Figure 39-176. Channel Input Filter
If the opposite edge appears on the input signal before validation (counter overflow), the
counter is reset. At the next input transition, the counter starts counting again. Any pulse
that is shorter than the minimum value selected by CHnFVAL[3:0] bits (× 4 system
clocks) is regarded as a glitch and is not passed on to the edge detector. A timing diagram
of the input filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed 3 rising edges of the system clock. If (CHnFVAL[3:0] ≠ 0000), then the
input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system clocks)
plus a further 4 rising edges of the system clock (two rising edges to the synchronizer,
one rising edge to the filter output plus one more to the edge detector). In other words,
CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on
the channel input.
The clock for the 5-bit counter in the channel input filter is the system clock divided by 4.
system clock divided by 4
channel (n) input
after the synchronizer
5-bit counter
CHnFVAL[3:0] = 0010
(binary value)
filter output
Time
Figure 39-177. Channel Input Filter Example
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
993