K60P100M100SF2RM Datasheet, PDF (772/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
32.6.1.2 Indirect Loads
For CAU load operations requiring a 32-bit input operand, the address contains the 9-bit
opcode to be passed to the MMCAU while the data is the 32-bit operand. Specifically,
the MMCAU address and data for these indirect writes is defined as:
31
28
24
20
16
MMCAU base address
12
1
8
4
CAU_CMD
0
00
Write address
31
28
24
20
16
12
8
4
Op1
Figure 32-17. Indirect loads
0
Write data
32.6.1.3 Indirect Stores
For CAU store operations, a PPB read is performed with the appropriate CAU store
register opcode embedded in the address. This appears as another indirect command. The
details are:
31
28
24
20
16
MMCAU base address
12
1
8
4
CAU_STR+Rn
0
00
Read address
31
28
24
20
16
12
8
4
CAx
Figure 32-18. Indirect store
0
Read data
32.6.2 MMCAU Integrity Checks
If an illegal operation or access is attempted, the PPB bus cycle is terminated with an
error response and the operation is aborted and not sent to the CAU.
The MMCAU performs a series of address and data integrity checks as described in the
following sections. The results of these checks are logically summed together, and if
appropriate, a PPB error termination is generated.
32.6.2.1 Address Integrity Checks
The MMCAU address checking includes the following. See Figure 32-15 for the
MMCAU memory map details.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
772
Freescale Semiconductor, Inc.