K60P100M100SF2RM Datasheet, PDF (1599/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
15–9
Reserved
8
CINT
7
CRM
6
CINS
5
BRR
4
BWR
Chapter 52 Secured digital host controller (SDHC)
SDHC_IRQSTAT field descriptions (continued)
Description
This read-only field is reserved and always has the value zero.
Card Interrupt
This status bit is set when an interrupt signal is detected from the external card. In 1-bit mode, the SDHC
will detect the Card Interrupt without the SD Clock to support wakeup. In 4-bit mode, the card interrupt
signal is sampled during the interrupt cycle, so the interrupt from card can only be sampled during
interrupt cycle, introducing some delay between the interrupt signal from the SDIO card and the interrupt
to the host system. Writing this bit to 1 can clear this bit, but as the interrupt factor from the SDIO card
does not clear, this bit is set again. In order to clear this bit, it is required to reset the interrupt factor from
the external card followed by a writing 1 to this bit.
When this status has been set, and the host driver needs to service this interrupt, the Card Interrupt
Signal Enable in the Interrupt Signal Enable register should be 0 to stop driving the interrupt signal to the
host system. After completion of the card interrupt service (It should reset the interrupt factors in the SDIO
card and the interrupt signal may not be asserted), write 1 to clear this bit, set the Card Interrupt Signal
Enable to 1, and start sampling the interrupt signal again.
0b No Card Interrupt
1b Generate Card Interrupt
Card Removal
This status bit is set if the Card Inserted bit in the Present State register changes from 1 to 0. When the
host driver writes this bit to 1 to clear this status, the status of the Card Inserted in the Present State
register should be confirmed. Because the card state may possibly be changed when the host driver
clears this bit and the interrupt event may not be generated. When this bit is cleared, it will be set again if
no card is inserted. In order to leave it cleared, clear the Card Removal Status Enable bit in Interrupt
Status Enable register.
0b Card state unstable or inserted
1b Card removed
Card Insertion
This status bit is set if the Card Inserted bit in the Present State register changes from 0 to 1. When the
host driver writes this bit to 1 to clear this status, the status of the Card Inserted in the Present State
register should be confirmed. Because the card state may possibly be changed when the host driver
clears this bit and the interrupt event may not be generated. When this bit is cleared, it will be set again if
a card is inserted. In order to leave it cleared, clear the Card Inserted Status Enable bit in Interrupt Status
Enable register.
0b Card state unstable or removed
1b Card inserted
Buffer Read Ready
This status bit is set if the Buffer Read Enable bit, in the Present State register, changes from 0 to 1.
Refer to the Buffer Read Enable bit in the Present State register for additional information.
0b Not ready to read buffer
1b Ready to read buffer
Buffer Write Ready
This status bit is set if the Buffer Write Enable bit, in the Present State register, changes from 0 to 1. Refer
to the Buffer Write Enable bit in the Present State register for additional information.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1599