K60P100M100SF2RM Datasheet, PDF (319/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

13.1.3.7 Software (SW) Reset
Chapter 13 Mode Controller
Setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control
Register forces a software reset on the device. A software reset resets of all major
components except for debug.
When the device is reset by a software reset, the SRSH[SW] bit is set.
13.1.3.8 Lock-Up Reset
When the processor’s built-in system state protection hardware detects the core is locked
up because of an unrecoverable exception, a lock-up reset occurs.
When a lock-up condition causes a reset, the SRSH[LOCKUP] bit is set.
13.1.3.9 EzPort Reset
The EzPort generates a system reset request following execution of a RESET command
via the EzPort interface. This method of reset allows the chip to boot from flash memory
after it has been programmed by an external source.
13.1.3.10 MDM-AP System Reset Request
A system reset is initiated by setting the System Reset Request bit in the MDM-AP
Control register. This is the primary method for resets via the debug interface. System
reset is held until this bit is cleared.
13.1.3.11 JTAG Reset
The JTAG module generates a system reset when certain IR codes are selected. This
functional reset is asserted when the EZPORT, EXTEST, HIGHZ and CLAMP
instructions are active. The reset source from the JTAG module is released when any
other IR code is selected. A JTAG reset causes the SRSH[JTAG] bit to set.
13.2 Mode Control Memory Map/Register Definition
The following table shows the registers related to the Mode Controller.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
319