K60P100M100SF2RM Datasheet, PDF (739/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
29.4.8 Extended Transfer Start/Address Latch Enable
The FB_TS/FB_ALE signal indicates that a bus transaction has begun and the address
and attributes are valid. By default, the FB_TS/FB_ALE signal asserts for a single bus
clock cycle. When CSCRn[EXTS] is set, the FB_TS/FB_ALE signal asserts and remain
asserted until the first positive clock edge after FB_CSn asserts. See the following figure.
NOTE
When EXTS is set, CSCRn[WS] must be programmed to have
at least one primary wait state.
FB_CLK
FB_A[Y]
Address
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
FB_CSn
AA=1
AA=0
FB_OEn
FB_BE/BWEn
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 29-53. Read-Bus Cycle with CSCRn[EXTS] = 1 (One Wait State)
29.4.9 Bus Errors
If the auto-acknowledge feature is not enabled for the address that generates the error, the
bus cycle can be terminated by asserting FB_TA. If the processor must manage a bus
error differently, asserting an interrupt to the core along with FB_TA when the bus error
occurs can invoke an interrupt handler.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
739