K60P100M100SF2RM Datasheet, PDF (1409/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
31
TCF
30
TXRXS
29
Reserved
28
EOQF
27
TFUF
26
Reserved
25
TFFF
24
Reserved
23
Reserved
22
Reserved
SPIx_SR field descriptions
Chapter 49 SPI (DSPI)
Transfer Complete Flag
Description
Indicates that all bits in a frame have been shifted out. TCF remains set until it is cleared by writing a 1 to
it.
0 Transfer not complete.
1 Transfer complete.
TX and RX Status
Reflects the run status of the DSPI.
0 Transmit and receive operations are disabled (DSPI is in stopped state).
1 Transmit and receive operations are enabled (DSPI is in running state).
This read-only field is reserved and always has the value zero.
End of Queue Flag
Indicates that the last entry in a queue has been transmitted when the DSPI is in master mode. The
EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and the end of the
transfer is reached. The EOQF bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing command.
1 EOQ is set in the executing SPI command.
Transmit FIFO Underflow Flag
Indicates an underflow condition in the TX FIFO. The transmit underflow condition is detected only for
DSPI blocks operating in slave mode and SPI configuration. TFUF is set when the TX FIFO of a DSPI
operating in SPI slave mode is empty and an external SPI master initiates a transfer. The TFUF bit
remains set until cleared by writing 1 to it.
0 No Tx FIFO underflow.
1 Tx FIFO underflow has occurred.
This read-only field is reserved and always has the value zero.
Transmit FIFO Fill Flag
Provides a method for the DSPI to request more entries to be added to the TX FIFO. The TFFF bit is set
while the TX FIFO is not full. The TFFF bit can be cleared by writing 1 to it or by acknowledgement from
the DMA controller to the TX FIFO full request. The Reset Value of this bit is 0 if MCR[MDIS] = 1. The
Reset Value of this bit is 1 if MCR[MDIS] = 0.
0 Tx FIFO is full.
1 Tx FIFO is not full.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1409