K60P100M100SF2RM Datasheet, PDF (1069/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
31–1
Reserved
0
TIF
Chapter 40 Periodic Interrupt Timer (PIT)
PIT_TFLGn field descriptions
Description
This read-only field is reserved and always has the value zero.
Timer Interrupt Flag.
TIF is set to 1 at the end of the timer period. This flag can be cleared only by writing it with 1. Writing 0
has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
0 Time-out has not yet occurred.
1 Time-out has occurred.
40.4 Functional Description
This section provides the functional description of the module.
40.4.1 General
This section gives detailed information on the internal operation of the module. Each
timer can be used to generate trigger pulses as well as to generate interrupts. Each
interrupt is available on a separate interrupt line.
40.4.1.1 Timers
The timers generate triggers at periodic intervals, when enabled. They load their start
values, as specified in their LDVAL registers, then count down until they reach 0. Then
they load their respective start value again. Each time a timer reaches 0, it will generate a
trigger pulse and set the interrupt flag.
All interrupts can be enabled or masked (by setting the TIE bits in the TCTRL registers).
A new interrupt can be generated only after the previous one is cleared.
If desired, the current counter value of the timer can be read via the CVAL registers.
The counter period can be restarted, by first disabling, then enabling the timer with the
TEN bit (see the following figure).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1069