K60P100M100SF2RM Datasheet, PDF (1595/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
1
HCKEN
0
IPGEN
Chapter 52 Secured digital host controller (SDHC)
SDHC_SYSCTL field descriptions (continued)
Description
• Continue request is just set, or
• This bit is set, or
• Card insertion is detected, or
• Card removal is detected, or
• Card external interrupt is detected, or
• 80 clocks for initialization phase is ongoing
0b SDHC clock will be internally gated off
1b SDHC clock will not be automatically gated off
System Clock Enable
If this bit is set, system clock will always be active and no automatic gating is applied. When this bit is
cleared,
system clock
will be automatically off when no data transfer is on the SD bus.
0b System clock will be internally gated off
1b System clock will not be automatically gated off
IPG Clock Enable
If this bit is set, bus clock will always be active and no automatic gating is applied.
The bus clock will be internally gated off, if none of the following factors are met:
• The cmd part is reset, or
• Data part is reset, or
• Soft reset, or
• The cmd is about to send, or
• Clock divisor is just updated, or
• Continue request is just set, or
• This bit is set, or
• Card insertion is detected, or
• Card removal is detected, or
• Card external interrupt is detected, or
• The SDHC clock is not gated off
NOTE: The bus clock will not be auto gated off if the SDHC clock is not gated off. So clearing only this
bit has no effect unless the PEREN bit is also cleared.
0b Bus clock will be internally gated off
1b Bus clock will not be automatically gated off
52.4.13 Interrupt Status Register (SDHC_IRQSTAT)
An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least
one of the status bits is set to 1. For all bits, writing 1 to a bit clears it; writing to 0 keeps
the bit unchanged. More than one status can be cleared with a single register write. For
Card Interrupt, before writing 1 to clear, it is required that the card stops asserting the
interrupt, meaning that when the Card Driver services the interrupt condition, otherwise
the CINT bit will be asserted again.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1595