K60P100M100SF2RM Datasheet, PDF (829/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 34 Analog-to-Digital Converter (ADC)
The PGA has only one voltage reference pair. The positive reference used is chip specific
and depends on the MCU configuration. Refer to the Chip Configuration chapter on the
PGA Voltage Reference specific to this MCU. The ground reference is the analog ground
for the PGA.
The ADC PGA register allows to control the PGA gain and modes of operation.
34.4.2 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module. This
clock source is then divided by a configurable value to generate the input clock to the
converter (ADCK). The clock is selected from one of the following sources by means of
the ADICLK bits.
• The bus clock. This is the default selection following reset.
• The bus clock divided by two. For higher bus clock rates, this allows a maximum
divide by 16 of the bus clock with using the ADIV bits.
• ALTCLK, as defined for this MCU. Refer to the Chip Configuration information.
• The asynchronous clock (ADACK). This clock is generated from a clock source
within the ADC module. Note that when the ADACK clock source is selected, it is
not required to be active prior to conversion start. When it is selected and it is not
active prior to a conversion start (ADACKEN=0), the asynchronous clock is
activated at the start of a conversion and shuts off when conversions are terminated.
In this case, there is an associated clock startup delay each time the clock source is
re-activated. To avoid the conversion time variability and latency associated with the
ADACK clock startup, set ADACKEN=1 and wait the worst case startup time of 5
µs prior to initiating any conversions using the ADACK clock source. Conversions
are possible using ADACK as the input clock source while the MCU is in Normal
Stop mode. Refer to Power Control for more information.
Whichever clock is selected, its frequency must fall within the specified frequency range
for ADCK. If the available clocks are too slow, the ADC may not perform according to
specifications. If the available clocks are too fast, the clock must be divided to the
appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1,
2, 4, or 8.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
829