K60P100M100SF2RM Datasheet, PDF (1025/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 39 FlexTimer (FTM)
39.4.12 Inverting
The invert functionality swaps the signals between channel (n) and channel (n+1)
outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0),
(DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1),
where m represents a channel pair. The INVm bit in INVCTRL register is updated with
its buffer value according to INVCTRL Register Synchronization
In high-true (ELSnB:ELSnA = 1:0) combine mode, the channel (n) output is forced low
at the beginning of the period (FTM counter = CNTIN), forced high at the channel (n)
match and forced low at the channel (n+1) match. If the inverting is selected, the channel
(n) output behavior is changed to force high at the beginning of the PWM period, force
low at the channel (n) match and force high at the channel (n+1) match. See the following
figure.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
before the inverting
channel (n+1) output
before the inverting
write 1 to INV(m) bit
INV(m) bit buffer
INVCTRL register
synchronization
INV(m) bit
channel (n) output
after the inverting
channel (n+1) output
after the inverting
NOTE
INV(m) bit selects the inverting to the pair channels (n) and (n+1).
Figure 39-225. Channels (n) and (n+1) Outputs After the Inverting in High-True
(ELSnB:ELSnA = 1:0) Combine Mode
Note that the ELSnB:ELSnA bits value should be consider since that they define the
active state of the channels outputs. In low-true (ELSnB:ELSnA = X:1) combine mode,
the channel (n) output is forced high at the beginning of the period, forced low at the
channel (n) match and forced high at the channel (n+1) match. In the case the inverting is
selected the channels (n) and (n+1) present waveforms as shown in the following figure.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1025