K60P100M100SF2RM Datasheet, PDF (185/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 5 Clock Distribution
5.6 Clock Gating
The clock to each module can be individually gated on and off using the SIM module's
SCGCx registers. These bits are cleared after any reset, which disables the clock to the
corresponding module to conserve power. Prior to initializing a module, set the
corresponding bit in SCGCx register to enable the clock. Before turning off the clock,
make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.7 Module clocks
The following table summarizes the clocks associated with each module.
Module
ARM Cortex-M4 core
NVIC
DAP
ITM
ETM
ETB
cJTAG, JTAGC
DMA
DMA Mux
Port control
Crossbar Switch
Peripheral bridges
MPU
LLWU, PMC, SIM
Mode controller
MCM
EWM
Watchdog timer
Table 5-2. Module clocks
Bus interface clock
Internal clocks
Core modules
System clock
Core clock
System clock
—
System clock
—
System clock
—
System clock
TRACE clock
System clock
—
—
—
System modules
System clock
—
Bus clock
—
Bus clock
LPO
System clock
System clock
—
Bus clock
System clock
—
Bus clock
LPO
Bus clock
—
System clock
—
Bus clock
LPO
Bus clock
LPO
Table continues on the next page...
I/O interface clocks
—
—
—
—
TRACE_CLKOUT
—
JTAG_CLK
—
—
—
—
—
—
—
—
—
—
—
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
185