K60P100M100SF2RM Datasheet, PDF (1609/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
52.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)
This register provides the host driver with information specific to the SDHC
implementation. The value in this register is the power-on-reset value, and does not
change with a software reset. Any write to this register is ignored.
Address: SDHC_HTCAPBLT is 400B_1000h base + 40h offset = 400B_1040h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
SRS
HSS
0
MBL
W
Reset 0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDHC_HTCAPBLT field descriptions
Field
31–27
Reserved
26
VS18
Description
This read-only field is reserved and always has the value zero.
Voltage Support 1.8 V
This bit shall depend on the host system ability.
25
VS30
0b 1.8 V not supported
1b 1.8 V supported
Voltage Support 3.0 V
This bit shall depend on the host system ability.
24
VS33
0b 3.0 V not supported
1b 3.0 V supported
Voltage Support 3.3 V
This bit shall depend on the host system ability.
0b 3.3 V not supported
1b 3.3 V supported
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1609