K60P100M100SF2RM Datasheet, PDF (191/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

5.7.9 UART clocking
Chapter 5 Clock Distribution
UART0 and UART1 modules operate from the core/system clock, which provides higher
performance level for these modules. All other UART modules operate from the bus
clock.
5.7.10 SDHC clocking
The SDHC module has four possible clock sources for the external clock source, as
shown in the following figure.
Core / system clock
MCGPLLCLK or
MCGFLLCLK
OSCERCLK
SDHC0_CLKIN
SDHC clock
SIM_SOPT2[SDHCSRC]
Figure 5-9. SDHC clock generation
5.7.11 I²S clocking
In addition to the bus clock, the I²S has a clock source for master clock generation. The
maximum frequency of this clock is 50 MHz. The master clock source can be derived
from several sources, as shown in the following figure.
Core/system clock
MCGPLLCLK or
MCGFLLCLK
SIM_CLKDIV2
[I2SFRAC,I2SDIV]
OSCERCLK
I2S_CLKIN
I²S master clock
SIM_SOPT2[I2SSRC]
Figure 5-10. I²S baud clock generation
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
191