K60P100M100SF2RM Datasheet, PDF (216/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
INTNMI
INTISR[239:0]
SLEEPING
SLEEPDEEP
NVIC
Interrupts
Sleep
Debug
Core
Instr.
Data
Cortex-M4
Trigger
AWIC
ETM
Trace port
(serial wire
or multi-pin)
ETB
TPIU
SW/
JTAG
SWJ-DP
FPB
Private Peripheral Bus
(internal)
AHB-AP
DWT
ITM
Bus
Matrix
APB
i/f
I-code bus
D-code bus
System bus
MCM
MMCAU
ROM
Table
Code bus
MDM-AP
Figure 9-1. Cortex-M4 Debug Topology
The following table presents a brief description of each one of the debug components.
Table 9-1. Debug Components Description
SWJ-DP+ cJTAG
AHB-AP
Module
JTAG-AP
ROM Table
Core Debug
CoreSight Trace Funnel (not shown in figure)
CoreSight Trace Replicator (not shown in figure)
ETM (Embedded Trace Macrocell)
CoreSight ETB (Embedded Trace Buffer)
ITM
Description
Modified Debug Port with support for SWD, JTAG, cJTAG
AHB Master Interface from JTAG to debug module and SOC
system memory maps
Bridge to DFT/BIST resources.
Identifies which debug IP is available.
Singlestep, Register Access, Run, Core Status
The CSTF combines multiple trace streams onto a single
ATB bus.
The ATB replicator enables two trace sinks to be wired
together and operate from the same incoming trace stream.
ETMv3.5 Architecture
Memory mapped buffer used to store trace data.
S/W Instrumentation Messaging + Simple Data Trace
Messaging + Watchpoint Messaging
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
216
Freescale Semiconductor, Inc.