K60P100M100SF2RM Datasheet, PDF (1698/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_IER field descriptions (continued)
Field
6
RFSEN
Description
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
5
TLSEN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
4
RLSEN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
3
RFF1EN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
2
RFF0EN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
1
TFE1EN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0
TFE0EN
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
1698
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.