K60P100M100SF2RM Datasheet, PDF (1041/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

FTM counter clock
write to MODE
set CAPTEST
Chapter 39 FlexTimer (FTM)
clear CAPTEST
CAPTEST bit
FTM counter 0x1053 ^{0x1054 0x1055}
write to CNT
CHnF bit
CnV
0x1056
0x78AC
write 0x78AC
0x0300
0x78AD
0x78AE0x78AF 0x78B0
0x78AC
NOTE
- FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and
(MOD = 0xFFFF)
- FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0)
Figure 39-243. Capture Test Mode
39.4.23 DMA
The channel generates a DMA transfer request according to DMA and CHnIE bits (see
the following table).
Table 39-247. Channel DMA Transfer Request
DMA
0
0
1
1
CHnIE
0
1
0
1
Channel DMA Transfer Request
The channel DMA transfer request is not
generated.
The channel DMA transfer request is not
generated.
The channel DMA transfer request is not
generated.
The channel DMA transfer request is generated
if (CHnF = 1).
Channel Interrupt
The channel interrupt is not generated.
The channel interrupt is generated if (CHnF = 1).
The channel interrupt is not generated.
The channel interrupt is not generated.
If DMA = 1, the CHnF bit is cleared either by channel DMA transfer done or reading
CnSC while CHnF is set and then writing a zero to CHnF bit according to CHnIE bit (see
the following table).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1041