K60P100M100SF2RM Datasheet, PDF (1054/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
The following figure shows motor jittering produced by the phase B and A pulses
respectively. The first highlighted transition causes a jitter on the FTM counter value near
the maximum count value (MOD). The second indicated transition occurs on phase A and
causes the FTM counter transition between the maximum and minimum count values
which are defined by MOD and CNTIN registers.
phase A
phase B
FTM counter
MOD
CNTIN
0x0000
Time
Figure 39-256. Motor Position Jittering Near Maximum and Minimum Count Value
The appropriate settings of the phase A and phase B input filters are important to avoid
glitches that may cause oscillation on the FTM counter value. The preceding figures
show examples of oscillations that can be caused by poor input filter setup. Thus, it is
important to guarantee a minimum pulse width to avoid these oscillations.
39.4.26 BDM Mode
When the chip is in BDM mode, the BDMODE[1:0] bits select the behavior of the FTM
counter, the CH(n)F bit, the channels output, and the writes to the MOD, CNTIN, and
C(n)V registers according to the following table.
Table 39-249. FTM Behavior When the Chip Is in BDM Mode
BDMMODE
00
FTM
Counter
Stopped
01
Stopped
CH(n)F Bit FTM Channels Output
Writes to MOD, CNTIN, and C(n)V Registers
can be set Functional mode
is not set
The channels outputs are forced
to their safe value according to
POLn bit
Writes to these registers bypass the registers
buffers
Writes to these registers bypass the registers
buffers
Table continues on the next page...
1054
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.