K60P100M100SF2RM Datasheet, PDF (386/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
MPU_EDRn field descriptions (continued)
Field
NOTE: All other encodings are reserved.
Description
0
ERW
000 User mode, instruction access
001 User mode, data access
010 Supervisor mode, instruction access
011 Supervisor mode, data access
Error read/write
Indicates the access type of the faulting reference.
0 Read
1 Write
18.3.4 Region Descriptor n, Word 0 (MPU_RGD_WORD0)
The first word of the region descriptor defines the 0-modulo-32 byte start address of the
memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
Addresses: 4000_D000h base + 400h offset + (16d × n), where n = 0d to 11d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SRTADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPU_RGDn_WORD0 field descriptions
Field
31–5
SRTADDR
4–0
Reserved
Start address
Description
Defines the most significant bits of the 0-modulo-32 byte start address of the memory region.
This read-only field is reserved and always has the value zero.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
386
Freescale Semiconductor, Inc.