K60P100M100SF2RM Datasheet, PDF (1497/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
6
RXEDGIF
5
MSBF
4
RXINV
3
RWUID
2
BRK13
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_S2 field descriptions (continued)
Description
0 No LIN break character has been detected.
1 LIN break character has been detected.
RxD Pin Active Edge Interrupt Flag
RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs.
RXEDGIF is cleared by writing a 1 to it. See RXEDGIF description for additional details.
NOTE: The active edge is only detected when in two wire mode and on receive data coming from the
RxD pin.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
Most Significant Bit First
Setting this bit reverses the order of the bits that are transmitted and received on the wire. This bit does
not affect the polarity of the bits, the location of the parity bit or the location of the start or stop bits.This bit
is automatically set or cleared when C7816[INIT] and C7816[ISO7816E] are enabled and an initial
character is detected.
0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the
start bit is identified as bit0.
1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting
of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6
depending on the setting of C1[M] and C1[PE].
Receive Data Inversion
Setting this bit, reverses the polarity of the received data input. In NRZ format, a one is represented by a
mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In
IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a
one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining
idle high for a one for inverted polarity.This bit is automatically set or cleared when C7816[INIT] and
C7816[ISO7816E] are enabled and an initial character is detected.
NOTE: Setting RXINV inverts the RxD input for: data bits, start and stop bits, break, and idle. When
C7816[ISO7816E] is set/enabled then only the data bits and the parity bit are inverted.
0 Receive data is not inverted.
1 Receive data is inverted.
Receive Wakeup Idle Detect
When RWU is set and WAKE is cleared, this bit controls whether the idle character that wakes the
receiver sets the S1[IDLE] bit.This bit must be cleared when C7816[ISO7816E] is set/enabled.
0 The S1[IDLE] bit is not set upon detection of an idle character.
1 The S1[IDLE] bit is set upon detection of an idle character.
Break Transmit Character Length
This bit determines whether the transmit break character is 10, 11, or 12 bits long, or 13 or 14 bits long.
Refer to Transmitting break characters for the length of the break character for the different
configurations. The detection of a framing error is not affected by this bit.
0 Break character is 10, 11, or 12 bits long.
1 Break character is 13 or 14 bits long.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1497