K60P100M100SF2RM Datasheet, PDF (1102/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low
+ high time. As the input clock period is fixed, the duty cycle resolution will be
proportional to the number of counts required to generate the desired carrier period.
42.7.3 Modulator
The modulator block controls the state of the infrared out signal (IRO) . The modulator
output is gated on to the IRO signal when the modulator/carrier generator is enabled .
When the modulator/carrier generator is disabled, the IRO signal is controlled by the state
of the IRO latch. OC[CMTPOL] enables the IRO signal to be active high or active low.
In CMT modes, the modulator functions as givenbelow:
• In Time mode, the modulator can gate the carrier onto the modulator output.
• In Baseband mode, the modulator can control the logic level of the modulator output.
• In FSK mode, the modulator can count carrier periods and instruct the carrier
generator to alternate between two carrier frequencies whenever a modulation period
(mark + space counts) expires.
The modulator provides a simple method to control protocol timing. The modulator has a
minimum resolution of 1.0 μs with an 8 MHz . It can count bus clocks (to provide real-
time control) or it can count carrier clocks (for self-clocked protocols).
The modulator includes a 17-bit down counter with underflow detection. The counter is
loaded from the 16-bit modulation mark period buffer registers, CMD1 and CMD2. The
most significant bit is loaded with a logic zero and serves as a sign bit. When the counter
holds a positive value, the modulator gate is open and the carrier signal is driven to the
transmitter block.
When the counter underflows, the modulator gate is closed and a 16-bit comparator is
enabled which compares the logical complement of the value of the down counter with
the contents of the modulation space period register which has been loaded from the
registers, CMD3 and CMD4.
When a match is obtained, the cycle repeats by opening the modulator gate, reloading the
counter with the contents of CMD1 and CMD2, and reloading the modulation space
period register with the contents of CMD3 and CMD4.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.