K60P100M100SF2RM Datasheet, PDF (916/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Definition
PDBx_CHnC1 field descriptions (continued)
Field
Description
These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0 PDB channel's corresponding pre-trigger disabled.
1 PDB channel's corresponding pre-trigger enabled.
38.3.6 Channel n Status Register (PDBx_CHS)
Addresses: PDB0_CH0S is 4003_6000h base + 14h offset = 4003_6014h
PDB0_CH1S is 4003_6000h base + 3Ch offset = 4003_603Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
CF
ERR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnS field descriptions
Field
31–24
Reserved
23–16
CF
15–8
Reserved
7–0
ERR
Description
This read-only field is reserved and always has the value zero.
PDB Channel Flags
The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to clear these bits.
This read-only field is reserved and always has the value zero.
PDB Channel Sequence Error Flags
Only the lower M bits are implemented in this MCU.
0 Sequence error not detected on PDB channel's corresponding pre-trigger.
1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered
for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by
one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's
corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1’s to clear the
sequence error flags.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
916
Freescale Semiconductor, Inc.