K60P100M100SF2RM Datasheet, PDF (1489/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
51.3.2 UART Baud Rate Registers: Low (UARTx_BDL)
This register, along with the BDH register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written. BDL is reset to a non-zero value, but after reset the
baud rate generator remains disabled until the first time the receiver or transmitter is
enabled (C2[RE] or C2[TE] bits are set)
Addresses: UART0_BDL is 4006_A000h base + 1h offset = 4006_A001h
UART1_BDL is 4006_B000h base + 1h offset = 4006_B001h
UART2_BDL is 4006_C000h base + 1h offset = 4006_C001h
UART3_BDL is 4006_D000h base + 1h offset = 4006_D001h
UART4_BDL is 400E_A000h base + 1h offset = 400E_A001h
Bit
7
6
5
4
3
2
1
0
Read
Write
SBR
Reset
0
0
0
0
0
1
0
0
UARTx_BDL field descriptions
Field
7–0
SBR
UART Baud Rate Bits
Description
The baud rate for the UART is determined by these 13 bits. See Baud rate generation for details
NOTE: The baud rate generator is disabled until the C2[TE] bit or the C2[RE] bit is set for the first time
after reset.The baud rate generator is disabled when SBR = 0.
NOTE: Writing to BDH has no effect without writing to BDL, since writing to BDH puts the data in a
temporary location until BDL is written.
NOTE: When the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate bits must be
even, the least significant bit is 0. Refer to MODEM register.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1489