K60P100M100SF2RM Datasheet, PDF (290/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: SIM_SCGC5 is 4004_7000h base + 1038h offset = 4004_8038h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
1
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
1
0
0
TSI
Reset 0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
SIM_SCGC5 field descriptions
Field
31–19
Reserved
18
Reserved
17–14
Reserved
13
PORTE
Description
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value one.
This read-only field is reserved and always has the value zero.
Port E Clock Gate Control
This bit controls the clock gate to the Port E module.
12
PORTD
0 Clock disabled
1 Clock enabled
Port D Clock Gate Control
This bit controls the clock gate to the Port D module.
11
PORTC
0 Clock disabled
1 Clock enabled
Port C Clock Gate Control
This bit controls the clock gate to the Port C module.
10
PORTB
0 Clock disabled
1 Clock enabled
Port B Clock Gate Control
This bit controls the clock gate to the Port B module.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
290
Freescale Semiconductor, Inc.