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K60P100M100SF2RM Datasheet, PDF (856/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual | |||
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6-bit DAC Key Features
⢠Selectable interrupt on rising edge, falling edge, or both rising or falling edges of
comparator output
⢠Selectable inversion on comparator output
⢠Comparator output may be:
⢠Sampled
⢠Windowed (ideal for certain PWM zero-crossing-detection applications)
⢠Digitally Filtered
⢠Filter can be bypassed
⢠Can be clocked via external SAMPLE signal or scaled bus clock
⢠External hysteresis can be used at the same time that the output filter is used for
internal functions.
⢠Two software selectable performance levels:
⢠Shorter propagation delay at the expense of higher power
⢠Low power, with longer propagation delay
⢠Support DMA transfer
⢠A comparison event can be selected to trigger a DMA transfer.
⢠Functional in all modes of operation.
⢠The window and filter functions are not available in Stop, VLPS, LLS and VLLSx
modes.
35.3 6-bit DAC Key Features
⢠6-bit resolution
⢠Selectable supply reference source
⢠Power down mode to conserve power when it is not being used
⢠Output can be routed to internal comparator input
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
856
Freescale Semiconductor, Inc.
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