K60P100M100SF2RM Datasheet, PDF (425/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 20 Direct memory access multiplexer (DMAMUX)
• Use explicit software re-activation. In this option, the DMA is configured to transfer
the data using both minor and major loops, but the processor is required to re-activate
the channel (by writing to the DMA registers) after every minor loop. For this option,
the DMA channel should be disabled in the DMA channel MUX.
• Use a "always enabled" DMA source. In this option, the DMA is configured to
transfer the data using both minor and major loops, and the DMA channel MUX does
the channel re-activation. For this option, the DMA channel should be enabled and
pointing to an "always enabled" source. Note that the re-activation of the channel can
be continuous (DMA triggering is disabled) or can use the DMA triggering
capability. In this manner, it is possible to execute periodic transfers of packets of
data from one source to another, without processor intervention.
20.5 Initialization/application information
This section provides instructions for initializing the DMA channel MUX.
20.5.1 Reset
The reset state of each individual bit is shown in Memory map/register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.
20.5.2 Enabling and configuring sources
Enabling a source with periodic triggering
1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point
4. Configure the corresponding timer
5. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set
Configure source #5 transmit for use with DMA channel 2, with periodic triggering
capability
1. Write 0x00 to CHCFG2 (base address + 0x02)
2. Configure channel 2 in the DMA, including enabling the channel
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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