K60P100M100SF2RM Datasheet, PDF (548/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
24.3.6 MCG Control 6 Register (MCG_C6)
Address: MCG_C6 is 4006_4000h base + 5h offset = 4006_4005h
Bit
7
6
5
4
3
2
1
0
Read
Write
LOLIE
PLLS
CME
VDIV
Reset
0
0
0
0
0
0
0
0
MCG_C6 field descriptions
Field
7
LOLIE
Loss of Lock Interrrupt Enable
Description
Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect
when LOLS is set.
6
PLLS
0 No interrupt request is generated on loss of lock.
1 Generate an interrupt request on loss of lock.
PLL Select
Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS
bit is cleared and PLLCLKEN is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is
disabled in all modes.
5
CME
0 FLL is selected.
1 _{PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference}
clock in the range of 2 - 4 MHz prior to setting the PLLS bit).
Clock Monitor Enable
Determines if a reset request is made following a loss of external clock indication. The CME bit should
only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE,
PEE, PBE, or BLPE). Whenever the CME bit is set to a logic 1, the value of the RANGE bits in the C2
register should not be changed. CME bit should be set to a logic 0 before the MCG enters any Stop
mode. Otherwise, a reset request may occur while in Stop mode. CME should also be set to a logic 0
before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
4–0
VDIV
0 External clock monitor is disabled.
1 Generate a reset request on loss of external clock.
VCO Divider
Selects the amount to divide the VCO output of the PLL. The VDIV bits establish the multiplication factor
(M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN or
PLLS), the VDIV value must not be changed when LOCK is zero.
Table 24-9. PLL VCO Divide Factor
VDIV
00000
Multiply
Factor
24
VDIV
01000
Multiply
Factor
32
VDIV
10000
Multiply
Factor
40
VDIV
11000
Multiply
Factor
48
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
548
Freescale Semiconductor, Inc.