K60P100M100SF2RM Datasheet, PDF (1494/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and registers
Addresses: UART0_S1 is 4006_A000h base + 4h offset = 4006_A004h
UART1_S1 is 4006_B000h base + 4h offset = 4006_B004h
UART2_S1 is 4006_C000h base + 4h offset = 4006_C004h
UART3_S1 is 4006_D000h base + 4h offset = 4006_D004h
UART4_S1 is 400E_A000h base + 4h offset = 400E_A004h
Bit
7
6
5
4
3
2
1
0
Read TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
Write
Reset
1
1
0
0
0
0
0
0
UARTx_S1 field descriptions
Field
7
TDRE
Transmit Data Register Empty Flag
Description
TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than
the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is
not included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data
register (D). For more efficient interrupt servicing all data except the final value to be written to the buffer
should written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the
clearing of the TRDE flag. This is more efficient since the TDRE will reassert until the watermark has been
exceeded so attempting to clear the TDRE every write will be ineffective until sufficient data has been
written.
0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
1 The amount of data in the transmit buffer is less than or equal to the value indicated by
TWFIFO[TXWATER] at some point in time since the flag has been cleared.
6
Transmit Complete Flag
TC
TC is cleared when there is a transmission in progress or when a preamble or break character is loaded.
TC is set when the transmit buffer is empty and no data, preamble, or break character is being
transmitted. When TC is set, the transmit data output signal becomes idle (logic 1). When 7816E is set/
enabled this bit is set after any NACK signal has been received but prior to any corresponding guard
times expiring. TC is cleared by reading S1 with TC set and then doing one of the following:
• Writing to the UART data register (D) to transmit new data
• Queuing a preamble by clearing and then setting the C2[TE] bit.
• Queuing a break character by writing 1 to SBK in C2
5
RDRF
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
Receive Data Register Full Flag
RDRF is set when the number of datawords in the receive buffer is equal to or more than the number
indicated by RWFIFO[RXWATER]. A dataword that is in the process of being received is not included in
the count. RDRF is prevented from setting while S2[LBKDE] is set. Additionally, when S2[LBKDE] is set,
datawords that are received will be stored in the receive buffer but will over-write each other. To clear
RDRF, read S1 when RDRF is set and then read the UART data register (D). For more efficient interrupt
and DMA operation all data except the final value is to be read from the buffer using D/C3[T8]/ED. The S1
should then be read and the final data value read, resulting in the clearing of the RDRF flag. Even if the
RDRF flag is set, data will continue to be received until an overrun condition occurs.
Table continues on the next page...
1494
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.