K60P100M100SF2RM Datasheet, PDF (566/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization / Application Information
e. PBE: Then loop until S[LOCK] is set, indicating that the PLL has acquired lock.
4. Lastly, PBE mode transitions into PEE mode:
a. C1 = 0x10
• C1[CLKS] set to 2'b00 in order to select the output of the PLL as the system
clock source.
b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to
feed MCGOUTCLK in the current clock mode.
• Now, With PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24,
MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
566
Freescale Semiconductor, Inc.