K60P100M100SF2RM Datasheet, PDF (1787/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 56
JTAG Controller (JTAGC)
56.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a
boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to
and output from the JTAGC block is communicated in serial format.
56.1.1 Block diagram
The following is a block diagram of the JTAG Controller (JTAGC) block.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1787