K60P100M100SF2RM Datasheet, PDF (702/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
FB_CSMRn field descriptions (continued)
Field
Description
Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip-
selects do not assert until V bit is set (except for FB_CS0, which acts as the global chip-select). Reset
clears each CSMRn[V].
NOTE: At reset, no chip-select other than FB_CS0 can be used until the CSMR0[V] is set. Afterward,
FB_CS[5:0] functions as programmed.
0 Chip select invalid
1 Chip select valid
29.3.3 Chip select control register (FB_CSCRn)
Each CSCRn controls the auto-acknowledge, address setup and hold times, port size,
burst capability, and number of wait states. To support the global chip-select (FB_CS0)
the CSCR0 reset values differ from the other CSCRs.
NOTE
The reset value of CSCR0 is as follows:
• Bits 31-24 are 0
• Bit 23-3 are device-dependent
• Bits 3-0 are 0
See the Chip Configuration details for your particular device for
information on the exact CSCR0 reset value.
Addresses: FB_CSCR0 is 4000_C000h base + 8h offset = 4000_C008h
FB_CSCR1 is 4000_C000h base + 14h offset = 4000_C014h
FB_CSCR2 is 4000_C000h base + 20h offset = 4000_C020h
FB_CSCR3 is 4000_C000h base + 2Ch offset = 4000_C02Ch
FB_CSCR4 is 4000_C000h base + 38h offset = 4000_C038h
FB_CSCR5 is 4000_C000h base + 44h offset = 4000_C044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SWS
W
0
WS
PS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FB_CSCRn field descriptions
Field
31–26
SWS
Secondary wait states
Description
If the SWSEN bit is set, the number of wait states inserted before an internal transfer acknowledge is
generated for a burst transfer except for the first termination, which is controlled by the wait state count
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
702
Freescale Semiconductor, Inc.