K60P100M100SF2RM Datasheet, PDF (217/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 9 Debug
Table 9-1. Debug Components Description (continued)
Module
DWT (Data and Address Watchpoints)
FPB (Flash Patch and Breakpoints)
TPIU (Trace Port Inteface Unit)
MCM (Miscellaneous Control Module)
Description
4 data and address watchpoints (configurable for less, but 4
seems to be accepted)
The FPB implements hardware breakpoints and patches
code and data from code space to system space.
The FPB unit contains two literal comparators for matching
against literal loads from Code space, and remapping to a
corresponding area in System space.
The FBP also contains six instruction comparators for
matching against instruction fetches from Code space, and
remapping to a corresponding area in System space.
Alternatively, the six instruction comparators can individually
configure the comparators to return a Breakpoint Instruction
(BKPT) to the processor core on a match, so providing
hardware breakpoint capability.
Synchronous Mode (5-pin) = TRACE_D[3:0] +
TRACE_CLKOUT
Synchronous Mode (3-pin) = TRACE_D[1:0] +
TRACE_CLKOUT
Asynchronous Mode (1-pin) = TRACE_SWO (available on
JTAG_TDO)
The MCM provides miscellaneous control functions including
control of the ETB and trace path switching.
9.1.1 References
For more information on ARM debug components, see these documents:
• ARMv7-M Architecture Reference Manual
• ARM Debug Interface v5.1
• ARM CoreSight Architecture Specification
• ARM ETM Architecture Specification v3.5
9.2 The Debug Port
The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in
the following figure:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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