K60P100M100SF2RM Datasheet, PDF (1352/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense
for Tx mailboxes. These bits are not transmitted. They are appended to the regular ID to
define the transmission priority. See Arbitration process.
ID — Frame Identifier
In Standard Frame format, only the 11 most significant bits (28 to 18) are used for frame
identification in both receive and transmit cases. The 18 least significant bits are ignored.
In Extended Frame format, all bits are used for frame identification in both receive and
transmit cases.
DATA BYTE 0-7 — Data Field
Up to eight bytes can be used for a data frame.
For Rx frames, the data is stored as it is received from the CAN bus. DATA BYTE (n) is
valid only if n is less than DLC as shown in the table below.
For Tx frames, the CPU prepares the data field to be transmitted within the frame.
Table 48-111. DATA BYTEs validity
DLC
0
1
2
3
4
5
6
7
8
Valid DATA BYTEs
none
DATA BYTE 0
DATA BYTE 0-1
DATA BYTE 0-2
DATA BYTE 0-3
DATA BYTE 0-4
DATA BYTE 0-5
DATA BYTE 0-6
DATA BYTE 0-7
48.3.57 Rx FIFO Structure
When the MCR[RFEN] bit is set, the memory area from 0x80 to 0xDC (which is
normally occupied by MBs 0 to 5) is used by the reception FIFO enginee.
The region 0x80-0x8C contains the output of the FIFO which must be read by the CPU as
a Message Buffer. This output contains the oldest message received and not read yet. The
region 0x90-0xDC is reserved for internal use of the FIFO engine.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.