K60P100M100SF2RM Datasheet, PDF (1440/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/Application Information
Push TX FIFO Register
TX FIFO Base
-
-
Entry A (first in)
Entry B
Entry C
Entry D (last in)
-
-
Transmit Next
Data Pointer
Shift Register
+1
TX FIFO Counter
-1
Figure 49-100. TX FIFO Pointers and Counter
SOUT
49.5.5.1 Address Calculation for the First-in Entry and Last-in Entry
in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following
equation:
The memory address of the last-in entry in the TX FIFO is computed by the following
equation:
TX FIFO Base - Base address of TX FIFO
TXCTR - TX FIFO Counter
TXNXTPTR - Transmit Next Pointer
TX FIFO Depth - Transmit FIFO depth, implementation specific
49.5.5.2 Address Calculation for the First-in Entry and Last-in Entry
in the RX FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following
equation:
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.