K60P100M100SF2RM Datasheet, PDF (1491/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
2
ILT
1
PE
0
PT
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_C1 field descriptions (continued)
Idle Line Type Select
Description
ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins
either after a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic
1s preceding the stop bit can cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
NOTE: In the case where UART is programmed with ILT = 1, a logic of 1'b0 is automatically shifted after
a received stop bit thus resetting the idle count.
NOTE: In the case where UART is programmed for IDLE line wakeup (RWU = 1 and WAKE = 0), ILT
has no effect on when the receiver starts counting logic 1s as idle character bits. In idle line
wakeup an idle character is recognized at anytime the receiver sees 10, 11, or 12 1s depending
on the M, PE, and C4[M10] bits.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
Parity Enable
Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position
immediately preceding the stop bit. This bit must be set when 7816E is set/enabled.
0 Parity function disabled.
1 Parity function enabled.
Parity Type
PT determines whether the UART generates and checks for even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.This bit must be
cleared when 7816E is set/enabled.
0 Even parity.
1 Odd parity.
51.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Addresses: UART0_C2 is 4006_A000h base + 3h offset = 4006_A003h
UART1_C2 is 4006_B000h base + 3h offset = 4006_B003h
UART2_C2 is 4006_C000h base + 3h offset = 4006_C003h
UART3_C2 is 4006_D000h base + 3h offset = 4006_D003h
UART4_C2 is 400E_A000h base + 3h offset = 400E_A003h
Bit
7
6
5
4
3
2
Read
TIE
TCIE
RIE
ILIE
TE
RE
Write
Reset
0
0
0
0
0
0
1
RWU
0
0
SBK
0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1491