K60P100M100SF2RM Datasheet, PDF (87/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
3.3.7 Memory Protection Unit (MPU) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge 0
Logical
Master
Logical
Master
Transfers
Register
access
Memory Protection
Unit (MPU)
Transfers
Slave
Slave
Logical
Master
Slave
Figure 3-11. Memory Protection Unit configuration
Table 3-16. Reference links to related information
Topic
Full description
System memory map
Clocking
Power management
Logical masters
Slave modules
Related module
Memory Protection Unit
(MPU)
Reference
MPU
System memory map
Clock distribution
Power management
Logical master assignments
Slave module assignments
3.3.7.1 MPU Slave Port Assignments
The memory-mapped resources protected by the MPU are:
Table 3-17. MPU Slave Port Assignments
Source
Crossbar slave port 0
Crossbar slave port 1
Code Bus
System Bus
Crossbar slave port 4
MPU Slave Port Assignment
MPU slave port 0
MPU slave port 1
MPU slave port 2
MPU slave port 3
MPU slave port 4
Destination
Flash Controller
SRAM backdoor
SRAM_L frontdoor
SRAM_U frontdoor
FlexBus
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
87